Continuous Time (CT) Sigma Delta Analogue-to-Digital and Digital-to-Analogue converters (ADCs), are considered the most appropriate type of ADC for high signal bandwidth applications. Indeed, CT sigma delta modulators have Factors Of Merit (FOM) from five to ten times better than their Discrete Time (DT) counterparts, and even better when compared to other Nyquist rate ADCs. The FOM indicates the amount of power needed to convert an analogue signal to the least-significant-bit (LSB) of a digital signal and thus reflects the power consumption of the converter for a given resolution (a given number of bits).
CT Sigma Delta modulators are of interest especially in the area of wireless communications, as they provide potential alternatives to bulky and high power consuming switched capacitor Sigma Delta modulators used in both I (In-phase) and Q (Quadrature-phase) channels of radio Intermediate Frequency (IF) sections. As recent 3rd generation (3G) wireless standards require higher IF signal bandwidth with little or no change in the signal Dynamic Range (DR), the power consumption will dramatically increase if switched capacitor sigma deltas continue to be used in future 3G IF sections.
Although CT sigma deltas are the most power efficient ADCs, nevertheless, some of their non-idealities severely limit their maximum achievable dynamic range. Two main non-idealities are the most limiting in CT sigma delta ADCs: (i) asymmetric rising and falling edges of the feedback path signal, and (ii) sampling clock jitter. These two problems, if addressed, would allow a CT sigma delta ADC to be widely used in all aspects of low power, high signal bandwidth and high sampling frequency applications. The asymmetric rising and falling edges error may be referred to as Intersymbol Interference error. The harmonic distortions it introduces may be also referred to as Intersymbol Distortions.
Referring firstly to FIG. 1, the general scheme of a known sigma delta modulator is constituted of a loop filter 10 (an integrator in general) of function H, an n-bit ADC 30 and an n-bit DAC 40, a feedback summation block 60 and two error components associated with non-idealities: a first error component 20 of the forward path (Eadc) and a second error component 50 of the feedback path (Edac). The filter 10 may be Discrete Time (DT) such as a switched capacitor filter, or continuous time such as an active RC or Gm-C filter.
The modulator of FIG. 1 is characterized by the following equation that expresses the modulator's output Y as function of the input X, the function H of the filter 10 and the error components Eadc and Edac:
                    Y        =                              X            ⁢                                                  ⁢                          H                              1                +                H                                              +                                    E              dac                        ⁢                          H                              1                +                H                                              +                                    E              adc                        ⁢                          1                              1                +                H                                                                        (                  Equation          ⁢                                          ⁢          1                )            
The function
  H      1    +    H  is a low-pass filter while
  1      1    +    H  is a high-pass filter. Thus, the non idealities of the forward path are high-pass filtered (noise-shaped) while the feedback path non-idealities are untouched and remain present in the signal baseband. Equation 1 shows clearly that the feedback path non-ideality errors Edac are present in the signal baseband.
In multi-bit sigma deltas, the multi-bit feedback DAC suffers from non-linearity errors due to component mismatches. These errors show up as harmonics in the signal baseband in accordance with Equation 1. This is the main reason that single bit modulators are the most widely used in sigma delta ADCs since a one-bit feedback DAC is inherently linear.
Feedback path asymmetric rising/falling edges and sampling clock jitter are by far the most critical feedback path non-idealities in CT sigma deltas. These non-idealities do not significantly affect DT sigma deltas thanks to the sample and hold feature inherent in switched capacitor circuits. The errors related to clock jitter are not in fact created inside the feedback path, but are rather produced by the circuitry that generates the clock. However the asymmetric rising/falling edges do originate from device mismatches in the feedback path. For the sake of simplicity, only single-bit sigma delta modulation is considered below. It will be understood that the following analysis for single-bit modulators can be extended to multi-bit modulators using well-known minor modifications.
The main sources of asymmetric rising/falling edges are mismatches between the path rising and falling time constants, the non-balanced or non-symmetric feedback DAC voltage thresholds, the non-symmetric spikes produced during signal transitions, etc.
Referring now to FIG. 2, there is shown a timing diagram which depicts an example of an ideal signal 70 and a real signal 80, both having a time period Ts. The real signal 80 has asymmetric rise/fall times 82 and 85 of tm. This error gives rise to even order harmonics including a strong DC component and also gives rise to large Intermodulation Distortions. It will be appreciated that even a small timing mismatch between rise and fall times can result in severe Signal to Noise and Distortion Ratio (SNDR) degradation.
From U.S. Pat. No. 5,196,853 there is known a robust technique that cancels distortion harmonics due to the asymmetric rising/falling edge mismatches. The technique, called Return to Zero (RZ), consists of returning to zero for half of each clock cycle the levels of a feedback DAC.
Referring now to FIG. 3 the RZ technique is shown. A non-RZ signal 90 exhibits usual behavior, including an asymmetric rising/falling edge 95. An RZ signal 100 cancels distortion harmonics due to the asymmetric rising/falling edges mismatches. The RZ signal 100 returns to zero for half of each clock cycle, and for the other half of each clock cycle, it follows the levels of the feedback DAC 40 of FIG. 1.
This method is widely used in data communications where such a signal coding results in reduced Intersymbol Interferences. The RZ operation makes all the signal levels sensitive to non-ideal rising and falling edges, in contrast to non-RZ (NRZ) operations where these non-idealities affect only signal levels that are adjacent to the transitions. In such a manner, the asymmetric transitions error appear as DC component error only, which is easily filtered with a digital high-pass filter in a subsequent portion of the circuitry.
However, the RZ technique, although it efficiently cancels the Intersymbol Interferences, suffers from many side effects. In fact, with the RZ technique the signal has now to settle and resolve in half a clock period. The settling process occurs at each clock cycle in contrast to the NRZ signals where it occurs only during signal transitions. The transition occurrence in RZ signals also occurs more often than in NRZ signals and leads to increased occurrence of settling solicitation. This gives rise to the following issues:    1. The problem that RZ is supposed to resolve reappears in high sampling frequencies since full settling may not occur during the Return to Zero phase.    2. The jitter in-band power increases by 12 dB (due the halved signal level duration needed in the RZ technique).    3. The loop filter H needs to settle within half a clock period rather than one period in NRZ, leading to doubled current consumption.    4. RZ technique doubles transition occurrence, leading to 6 dB increase in the power of transition spikes and errors.    5. RZ implementation requires additional circuitry that leads to additional current consumption and parasitics (e.g., switch charge injection, spikes).    6. The RZ technique does not compensate for a DC component; in fact, it shifts the power of the even order harmonics to DC.
A need therefore exists for compensation of feedback path non-idealities of continuous time sigma delta ADCs wherein al least some of the abovementioned disadvantage(s) may be alleviated.